Generate File Name in Verilog

When using $memread[b|h] in Verilog, we always try to load many files for memory initialization.
We can generate the filename as following:

reg [50*8:0] FullFileName;
reg [5*8:0] FileExt;
reg [5*8:0] FileName;

initial
begin
i=0;
FileName = "MemData";
FileExt = ".dat";

repeat(10)
begin
$sformat(FullFileName,"%0s%0d%0s",FileName,i,FileExt); //o is "zero"
$memreadb(FullFileName,MyMem);
i = i + 1;
.......
end
.....
end

So far, only test in ModelSim 6.2.